The present invention relates to clock recovery and data extraction and, more particularly, to clock recovery and data extraction using digital circuitry.
A typical disk drive includes one or more disks mounted for rotation on a hub or spindle. A typical disk drive also includes a transducer supported by a hydrodynamic air bearing which flies above each disk. The transducer and the hydrodynamic air bearing are collectively referred to as a data head. A drive controller is conventionally used for controlling the disk drive based on commands received from a host system. The drive controller controls the disk drive to retrieve information from the disks and to store information on the disks.
In one conventional disk drive, an electromechanical actuator operates within a negative feedback, closed-loop servo system. The actuator moves the data head radially over the disk surface for track seek operations and holds the transducer directly over a track on the disk surface for track following operations.
Information is typically stored in concentric tracks on the surface of the disks by providing a write signal to the data head to write information on the surface of the disk representing the data to be stored. In retrieving data from the disk, the drive controller controls the electromechanical actuator so that the data head flies above the disk and generates a read signal based on information stored on the disk. The read signal is typically conditioned and then decoded by the drive controller to recover the data.
A typical read channel includes the data head, preconditioning logic (such as preamplification circuitry and filtering circuitry), a data detector and recovery circuit, and error detection and correction circuitry. The read channel is typically implemented in a drive controller associated with the disk drive. This data is typically implemented on integrated circuits and, correspondingly, the clock distribution within the integrated circuit requires precise phase correlation. This is to ensure that there is proper setup and processing of the digital information within the integrated circuit.
The timing requirements of multiple integrated circuits of a digital system also require equally precise phase correlation. Reliable operation of the integrated circuit depends on the data being stable when a clock signal is received. If the clock signal is out of phase, then the data may no longer be valid. This is also true when transferring signals between multiple integrated circuits.
Digital signals propagate through a plurality of combinatorial gate logic, shift registers, storage registers, transmission media, and encounter other propagation delays due to circuit capacitance, inductance, and signal path distances within or between integrated circuits. All electronic circuits have resistance, inductance, and capacitance inherent within the physical structure of the electronic circuit. Integrated circuit devices have predominately resistance and capacitance. The resistance (R) and capacitance (C) create an RC time constant delay to a fast rising edge square wave such as a clock signal. When clock signal delays are different between different areas of the integrated circuit, then the difference between the signal delays or phase difference is called xe2x80x9cskew.xe2x80x9d Differences in clock signal delays are usually caused by differences in capacitance associated with the different circuit loads requiring the clock signal. As speed of digital signals increases, skew becomes a more significant problem.
Digital phase-locked loops (DPLL) or, more generally, phase-locked loops (PLL) are utilized with ASIC state machines in both read channel, communication and computer applications. The DPLL includes a series of delay elements that are selectable. A received digital signal is compared against a reference clock signal. The phase difference between the signals is determined by a phase detector of the DPLL, and the appropriate amount of delay that is added to the digital signal until the phase difference between signals is minimal or substantially 90 degrees in accordance with the particular application. The DPLL does not change the received digital signal; it only delays the signal by a discrete amount.
Precise control of the phase delay of digital signals in a digital system such as a DPLL requires a plurality of digital phase delay circuits. The number of delay circuits required depends on the phase granularity required in the system. For example, one degree phase increments requires utilizing 359 different delay circuits. These delay circuits may be configured into coarse and fine phase delay steps when the coarse steps are made in one delay circuit and fine steps between each coarse step are made in another delay circuit.
A PLL, which is the more general case of a DPLL, usually includes a phase comparator to receive incoming data, typically in Manchester format. The phase comparator determines whether the received data lags or leads a reference clock. When the data lags the reference clock, the comparator issues a down adjust signal to a charge pump and, conversely, when the data leads the reference clock, the phase comparator issues an up adjust signal to the charge pump. The charge pump then removes or adds charge to the circuit, acting like an integrator by issuing a voltage signal to a voltage-to-frequency oscillator (VCO) circuit.
The VCO circuit receives the voltage signal and adjusts its frequency of operation accordingly. However, data tends to jitter in real system operation. Edges of data can bounce around within a limit of 18 Ns and still be within the IEEE specifications for Manchester data. A feedback loop of the PLL is intended to make the adjustment to the VCO to track the average mean of the jittering.
The PLL further includes a loop filter that is typically a low-pass filter and acts as a dampening circuit.
FIG. 1 illustrates an implementation of a DPLL. The structure of the PLL includes a loop filter 100 designated by LF. The VCO is the voltage-controlled oscillator 110, and the phase error detector 120 is designated by PED. The phase error detector 120 provides an estimate of the timing phase error. Typically, the loop filter 100 and voltage-controlled oscillator 110 has low-pass characteristics so that rapid variation in the phase error estimate can be removed. Thus, the sample phase illustrated by switch 130 is adjusted in accordance with the output of the voltage-controlled oscillator 110.
For high-speed applications, various implementation techniques, such as parallel processing and pipelining, have been adopted for speeding up the operation of the hardware devices. These implementation techniques, however, create increased hardware complexity and significant loop latency.
With the present invention, the input signal of the PLL can be resampled (decimated) with a lower rate, and then the PLL operates with a lower clock rate without affecting the overall performance. The PLL attempts to detect phase variation which is typically slow with respect to the sampling rate. Therefore, the present invention can employ a resampling rate which is lowered significantly from the sampling rate without affecting the performance of the PLL. This technique increases hardware speed without increasing hardware complexity and latency. The present invention illustrates a half-sampling rate; however, a xc2xc or ⅓ sampling rate could be implemented without departing from the scope of the present invention.